VHDL:如何使用两个常规的4位加法器来设计一个8位BCD计数器？

signal counter : std_logic_vector(7 downto 0);

signal clk : std_logic;
signal reset : std_logic;

library ieee;
use ieee.std_logic_1164.all;

entity BCD_Counter is
  port (
    clk   : in std_logic;
    reset : in std_logic;
    count : out std_logic_vector(7 downto 0)
  );
end entity BCD_Counter;

architecture Behavioral of BCD_Counter is
  signal counter_4bit1 : std_logic_vector(3 downto 0);
  signal counter_4bit2 : std_logic_vector(3 downto 0);
begin
  process(clk, reset)
  begin
    if reset = '1' then
      counter_4bit1 <= "0000";
      counter_4bit2 <= "0000";
    elsif rising_edge(clk) then
      if counter_4bit1 = "1001" then
        counter_4bit1 <= "0000";
        if counter_4bit2 = "1001" then
          counter_4bit2 <= "0000";
        else
          counter_4bit2 <= counter_4bit2 + 1;
        end if;
      else
        counter_4bit1 <= counter_4bit1 + 1;
      end if;
    end if;
  end process;

  count <= counter_4bit2 & counter_4bit1;
end architecture Behavioral;