编写一个vhdl程序来模拟一个带有寄存器输出和复位的4x2编码器

library ieee;
use ieee.std_logic_1164.all;

entity encoder is
    port (
        input : in std_logic_vector(3 downto 0);
        output : out std_logic_vector(1 downto 0);
        register_output : out std_logic;
        reset : in std_logic
    );
end entity encoder;

architecture behavioral of encoder is
    signal encoded_output : std_logic_vector(1 downto 0);
    signal register_value : std_logic_vector(1 downto 0);
begin
    process (input, reset)
    begin
        if reset = '1' then
            register_value <= "00";
        else
            case input is
                when "0001" =>
                    encoded_output <= "00";
                when "0010" =>
                    encoded_output <= "01";
                when "0100" =>
                    encoded_output <= "10";
                when "1000" =>
                    encoded_output <= "11";
                when others =>
                    encoded_output <= "00";
            end case;
            
            register_value <= encoded_output;
        end if;
    end process;
    
    output <= encoded_output;
    register_output <= register_value(0);
end architecture behavioral;