如何将奇偶校验位附加到给定的4位std_logic_vector？

library ieee;
use ieee.std_logic_1164.all;

entity parity_check is
    port (
        input_vector : in std_logic_vector(3 downto 0);
        output_vector : out std_logic_vector(4 downto 0)
    );
end entity parity_check;

architecture behavioral of parity_check is
    signal count : integer := 0;
    signal parity_bit : std_logic := '0';
begin
    process(input_vector)
    begin
        -- 计算1的个数
        for i in input_vector'range loop
            if input_vector(i) = '1' then
                count := count + 1;
            end if;
        end loop;
        
        -- 确定奇偶校验位的值
        if count mod 2 = 1 then
            parity_bit <= '1';
        else
            parity_bit <= '0';
        end if;
        
        -- 创建新的std_logic_vector
        output_vector <= input_vector & parity_bit;
    end process;
end architecture behavioral;