如何在VHDL中创建异步边缘检测器？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AsyncEdgeDetector is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           input_signal : in STD_LOGIC;
           edge_detected : out STD_LOGIC);
end AsyncEdgeDetector;

architecture Behavioral of AsyncEdgeDetector is
    signal previous_input : STD_LOGIC := '0';
begin
    process(input_signal, reset)
    begin
        if reset = '1' then
            previous_input <= '0';
            edge_detected <= '0';
        else
            if input_signal /= previous_input then
                edge_detected <= '1';
                previous_input <= input_signal;
            else
                edge_detected <= '0';
            end if;
        end if;
    end process;
end Behavioral;