如何在仅使用时钟的Verilog中设计串并缓冲器？

module SerialParallelBuffer (
  input wire Data_In,
  input wire Clock,
  input wire Reset,
  output wire Data_Out
);

reg [7:0] Serial_Register;
wire [7:0] Parallel_Data;

always @(posedge Clock or posedge Reset) begin
  if (Reset)
    Serial_Register <= 8'h00;
  else
    Serial_Register <= {Serial_Register[6:0], Data_In};
end

assign Parallel_Data = Serial_Register;

assign Data_Out = Parallel_Data;

module SerialParallelBuffer (
  input wire Data_In,
  input wire Clock,
  input wire Reset,
  output wire Data_Out
);
  
  reg [7:0] Serial_Register;
  wire [7:0] Parallel_Data;

  always @(posedge Clock or posedge Reset) begin
    if (Reset)
      Serial_Register <= 8'h00;
    else
      Serial_Register <= {Serial_Register[6:0], Data_In};
  end

  assign Parallel_Data = Serial_Register;
  assign Data_Out = Parallel_Data;

endmodule