基于Verilog的多路复用器4x1测试平台

module mux4x1(
    input wire [3:0] data_in,  // 4位输入信号
    input wire [1:0] sel,      // 2位选择信号
    output reg data_out        // 1位输出信号
);

always @(*) begin
    case (sel)
        2'b00: data_out = data_in[0];
        2'b01: data_out = data_in[1];
        2'b10: data_out = data_in[2];
        2'b11: data_out = data_in[3];
        default: data_out = 1'b0;
    endcase
end

endmodule

module mux4x1_tb;
    reg [3:0] data_in;
    reg [1:0] sel;
    wire data_out;

    mux4x1 uut (
        .data_in(data_in),
        .sel(sel),
        .data_out(data_out)
    );

    initial begin
        // 初始化输入信号
        data_in = 4'b0000;
        sel = 2'b00;

        // 测试不同输入和选择信号的组合
        #10 data_in = 4'b0001; sel = 2'b01;
        #10 data_in = 4'b0010; sel = 2'b10;
        #10 data_in = 4'b0011; sel = 2'b11;
        #10 $finish;
    end

    initial begin
        $dumpfile("mux4x1.vcd");
        $dumpvars(0, mux4x1_tb);
    end
endmodule