4位加减器Verilog代码错误

module adder_subtractor (
  input [3:0] A, B,
  input SUB,
  output [4:0] SUM,
  output CARRY_OUT,
  output OVERFLOW
);

  wire CARRY_IN;
  wire [4:0] ADD;
  wire [4:0] SUB_OUT;
  
  assign CARRY_IN = 0;
  
  adder_4bit adder (
    .A(A),
    .B(B),
    .CARRY_IN(CARRY_IN),
    .SUM(ADD)
  );
  
  subtractor_4bit subtractor (
    .A(A),
    .B(B),
    .CARRY_IN(CARRY_IN),
    .SUM(SUB_OUT)
  );
  
  assign SUM = SUB ? SUB_OUT : ADD;
  assign CARRY_OUT = ADD[4];
  assign OVERFLOW = (A[3] & B[3] & ~SUM[3]) | (~A[3] & ~B[3] & SUM[3]);
  
endmodule

module adder_4bit (
  input [3:0] A, B,
  input CARRY_IN,
  output [4:0] SUM
);

  wire [3:0] CARRY;
  
  assign SUM[0] = A[0] ^ B[0] ^ CARRY_IN;
  assign CARRY[0] = (A[0] & B[0]) | (CARRY_IN & (A[0] ^ B[0]));
  
  assign SUM[1] = A[1] ^ B[1] ^ CARRY[0];
  assign CARRY[1] = (A[1] & B[1]) | (CARRY[0] & (A[1] ^ B[1]));
  
  assign SUM[2] = A[2] ^ B[2] ^ CARRY[1];
  assign CARRY[2] = (A[2] & B[2]) | (CARRY[1] & (A[2] ^ B[2]));
  
  assign SUM[3] = A[3] ^ B[3] ^ CARRY[2];
  assign CARRY[3] = (A[3] & B[3]) | (CARRY[2] & (A[3] ^ B[3]));
  
  assign SUM[4] = CARRY[3];
  
endmodule

module subtractor_4bit (
  input [3:0] A, B,
  input CARRY_IN,
  output [4:0] SUM
);

  wire [3:0] B_COMPLEMENT;
  
  assign B_COMPLEMENT = ~B + 1;
  
  adder_4bit adder (
    .A(A),
    .B(B_COMPLEMENT),
    .CARRY_IN(CARRY_IN),
    .SUM(SUM)
  );
  
endmodule