uvm中的tlm通信机制

class in_monitor#(parameter WIDTH=8,parameter DEPTH=16) extends uvm_monitor#(in_transaction);

    in_interface              in_bus;

    logic                     winc;
    logic                     ricn;
    bit[WIDTH-1:0]            wdata;

    uvm_tlm_analysis_fifo#(in_transaction)          in_mon2rm_fifo;

    `uvm_component_utils(in_monitor)

    extern virtual function new(string name = "in_monitor",uvm_component parent);
    extern virtual function void build_phase(uvm_phase phase);
    extern virtual task main_phase(uvm_phase phase);

endclass:in_monitor

function in_monitor::new(string name, uvm_component parent);

    super.new(name,parent);

endfunction:new

function void in_monitor::build_phase(uvm_phase phase);

    super.build_phase(phase);
    if(!uvm_config_db#(virtual in_interface)::get(this,"","in_bus",this.in_bus))begin
        `uvm_fatal("","")
    end

endfunction:build_phase

task in_monitor::main_phase(uvm_phase phase);

    automatic in_transaction            req;
    super.main_phase(phase);
    while(1)begin
        @this.in_bus.mon_cb;
        this.winc <= this.in_bus.winc;
        this.rinc <= this.in_bus.rinc;
        this.wdata <= this.in_bus.wdata;

        this.req = in_transaction::type_id::create("req",this);
        this.req.winc = this.winc;
        this.req.rinc = this.rinc;
        this.req.wdata = this.wdata;

        if(this.in_mon2rm_fifo != null)begin
            this.in_mon2rm_fifo.write(this.req);
        end

    end
endtask:main_phase