RVB 23 profile

RVB23 Profiles

Introduction

This document specifies the RVB23 profile family. RVB23 is the first major release of the RVB series of RISC-V Application Processor Profile.

本文档属于 RVB23 profile 系列。RVB23 是 RISC-V 应用处理器 profile 系列的第一个主要版本。

RVB profiles are intended to be used for customized 64-bit application processors that will run rich OS stacks, but usually as a custom build of standard OS source-code distributions. The approach is to provide a large guaranteed set of relatively inexpensive and/or widely beneficial features but allow optionality for more expensive and/or more targeted extensions.

RVB profile 旨在用于定制的 64 位应用处理器，这些处理器将运行丰富的操作系统堆栈，但通常是标准操作系统源代码分发的自定义构建。目标是提供一组大量的、相对廉价和/或广泛有益的特性，但允许更昂贵和/或更有针对性的 extensions。

Unlike the RVA profiles, it is explicitly a non-goal of RVB profiles to provide a single standard ISA interface supporting a wide variety of binary kernel and binary application software distributions. However, individual software ecosystems may build upon RVB profiles to produce a more targeted standard interface for a certain market.

不同于 RVA profile 系列，RVB profile 系列明确不提供支持各种二进制内核和二进制应用软件分发的单一标准 ISA 接口。然而，个别软件生态系统可以基于 RVB profile 系列构建更有针对性的标准接口，以满足特定市场的需求。

Profile-Defined Extensions

RVB23 has been ratified alongside RVA23, and the same set of new profile-defined extensions defined in RVA23 are present in RVB23. These profile-defined extensions will soon move to the combined ISA manual. Future releases of RVA and RVB profiles might not proceed through ratification at the same time, and future profile-defined extensions will be presented as an edit to the combined ISA manual.

RVB23 与 RVA23 同时获得批准，RVA23 中定义的一组新的 profile-defined extensions 也出现在 RVB23 中。这些 profile-defined extensions 将很快移至合并的 ISA 手册。未来的 RVA 和 RVB profile 版本可能不会同时获得批准，并且未来的 profile-defined extensions 将作为合并 ISA 手册的编辑呈现。

RVB23 Profiles

Only user-mode (RVB23U64) and supervisor-mode (RVB23S64) profiles are specified in this family.

RVB23 profile 系列中只指定了 u-mode（RVB23U64）和 s-mode（RVB23S64）profile。

RVB23U64 Profile

The RVB23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit RVB applications processors.

RVB23U64 profile 指定了 64 位 RVB 应用处理器中 u-mode 执行环境可用的 ISA 特性。

RVB23U64 Mandatory Base

RV64I is the mandatory base ISA for RVB23U64 and is little-endian. As per the unprivileged architecture specification, the ECALL instruction causes a requested trap to the execution environment.

RV64I 是 RVB23U64 的强制基本 ISA，并且是小端的。根据非特权架构规范，ECALL 指令导致对执行环境的 trap。

RVB23U64 Mandatory Extensions

The following mandatory extensions in RVB23U64 were also mandatory in

RVA22U64.

以下在 RVB23U64 中强制的扩展在 RVA22U64 中也是强制的。

• M Integer multiplication and division.

M 整数乘除

• A Atomic instructions.

A 原子指令

• F Single-precision floating-point instructions.

F 单精度浮点指令

• D Double-precision floating-point instructions.

D 双精度浮点指令

• C Compressed instructions.

C 压缩指令

• B Bit-manipulation instructions.

B 位操作指令

• Zicsr CSR instructions. These are implied by presence of F.

Zicsr CSR 指令。这些是由 F 的存在隐含的。

• Zicntr Base counters and timers.

Zicntr 基本计数器和计时器

• Zihpm Hardware performance counters.

Zihpm 硬件性能计数器

• Ziccif Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVB23) are atomic.

Ziccif 具有 cacheability 和 coherence PMAs 的主存储区域必须支持指令获取，并且对于最小对齐 2 的幂大小的任何指令获取，最大为 min(ILEN,XLEN)（即，对于 32 bit RVB23）是原子的。

• Ziccrse Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.

Ziccrse 具有 cacheability 和 coherence PMAs 的主存储区域必须支持 RsrvEventual。

• Ziccamoa Main memory regions with both the cacheability and coherence PMAs must support all atomics in A.

Ziccamoa 具有 cacheability 和 coherence PMAs 的主存储区域必须支持 A 中的所有原子操作。

• Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.

Zicclsm 对具有 cacheability 和 coherence PMAs 的主存储区域的不对齐加载和存储必须得到支持。

• Za64rs Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes.

Za64rs Reservation sets 是连续的，自然对齐的，最大为 64 bytes

• Zihintpause Pause hint.

Zihintpause 暂停提示

• Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.

Zic64b 缓存块大小必须为 64 bytes，在地址空间中自然对齐。

• Zicbom Cache-block management instructions.

Zicbom 缓存块管理指令

• Zicbop Cache-block prefetch instructions.

Zicbop 缓存块预取指令

• Zicboz Cache-block zero instructions.

Zicboz 缓存块零指令

• Zkt Data-independent execution latency.

Zkt 数据无关的执行延迟

The following mandatory extensions are also present in RVA23U64:

以下强制扩展在 RVA23U64 中也存在：

• Zihintntl Non-temporal locality hints.
• Zicond Integer conditional operations.

Zicond 整数条件操作

• Zimop May-be-operations.

Zimop May-be 操作

• Zcmop Compressed may-be-operations.

Zcmop 压缩的 May-be 操作

• Zcb Additional compressed instructions.

Zcb 额外的压缩指令

• Zfa Additional floating-point instructions.

Zfa 额外的浮点指令

• Zawrs Wait-on-reservation-set instructions.

Zawrs 等待保留集指令

RVB23U64 Optional Extensions

RVB23U64 has 18 profile options listed below.

RVB23U64 有下面列出的 18 个 profile 选项。

Localized Options

The following extensions are localized options in both RVA23U64 and RVB23U64:

下列 extensions 是 RVA23U64 和 RVB23U64 中的 localized options：

• Zvkng Vector crypto NIST Algorithms with GCM.

Zvkng 使用 GCM 的Vector crypto NIST 算法

• Zvksg Vector crypto ShangMi Algorithms with GCM.

Zvksg 使用 GCM 的 Vector crypto ShangMi 算法

The following extensions options are localized options in RVB23U64 but

are not present in RVA23U64:

下列 extensions options 是 RVB23U64 中的 localized options，但在 RVA23U64 中不存在：

• Zvkg Vector GCM/GMAC instructions.

Zvkg Vector GCM/GMAC 指令

• Zvknc Vector crypto NIST algorithms with carryless multiply.

Zvknc 带有无进位乘法的 Vector crypto NIST 算法

• Zvksc Vector crypto ShangMi algorithms with carryless multiply.

Zvksc 带有无进位乘法的 Vector crypto ShangMi 算法

NOTE: RVA profiles mandate the higher-performing but more expensive GHASH options when adding vector crypto. To reduce implementation cost, RVB profiles also allow these carryless multiply options (Zvknc and Zvksc) to implement GCM efficiently, with GHASH available as a separate option.

NOTE: RVA profile 在添加矢量 crypto 时强制使用性能更高但成本也更高的 GHASH 选项。为了降低实现成本，RVB profile 也允许这些 carryless multiply 选项（Zvknc 和 Zvksc）有效地实现 GCM，GHASH 可作为单独的选项。

• Zkn Scalar crypto NIST algorithms.

Zkn Scalar crypto NIST 算法

• Zks Scalar crypto ShangMi algorithms.

Zks Scalar crypto ShangMi 算法

NOTE: RVA23 profiles drop support for scalar crypto as an option, as

the vector extension is now mandatory in RVA23. RVB23 profiles

support scalar crypto, as the vector extension is optional in RVB23.

NOTE: RVA23 profile 放弃了标量 crypto 作为选项的支持，因为矢量扩展现在在 RVA23 中是强制的。

RVB23 profile 支持标量 crypto，因为矢量扩展在 RVB23 中是可选的。

Development Options

The following are new development options intended to become mandatory in a later RVB profile:

下列是新的开发选项，预计在以后的 RVB profile 中变为强制选项：

• Zabha Byte and halfword atomic memory operations.

Zabha 字节和半字原子内存操作

• Zacas Compare-and-Swap instructions.

Zacas Compare-and-Swap 指令

• Ziccamoc Main memory regions with both the cacheability and coherence PMAs must provide AMOCASQ level PMA support.

Ziccamoc 具备 cacheability 和 coherence PMAs 的主存储区域必须提供 AMOCASQ 级别的 PMA 支持

• Zama16b Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.

Zama16b 对于不跨越自然对齐的 16 字节边界的主存储区域的不对齐加载、存储和 AMO 操作是原子的

Expansion Options

The following are expansion options in RVB23U64, but are mandatory in

RVA23U64.

以下为 RVB23U64 中的 expansion options，但在 RVA23U64 中是强制的

• Zfhmin Half-precision floating-point.

Zfhmin 半精度浮点

• V Vector extension.

V 矢量扩展

NOTE: Unclear if other Zve* extensions should also be supported in RVB.

NOTE: 目前尚不确定 RVB 是否应该支持其他 Zve* 扩展。

• Zvfhmin Vector minimal half-precision floating-point.

Zvfhmin 矢量最小半精度浮点

• Zvbb Vector basic bit-manipulation instructions.

Zvbb 矢量基本位操作指令

• Zvkt Vector data-independent execution latency.

Zvkt 矢量数据无关的执行延迟

• Supm Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

Supm 指针掩码，执行环境提供一种选择 PMLEN=0 和 PMLEN=7 的方法

The following extensions are expansion options in both RVA23U64 and RVB23U64:

以下 extensions 是 RVA23U64 和 RVB23U64 中的 expansion options：

• Zfh Scalar half-precision floating-point.
• Zbc Scalar carryless multiplication.
• Zicfilp Landing Pads.
• Zicfiss Shadow Stack.
• Zvfh Vector half-precision floating-point.
• Zfbfmin Scalar BF16 converts.
• Zvfbfmin Vector BF16 converts.
• Zvfbfwma Vector BF16 widening mul-add.

The following are expansion options for RVB23U64 as they are not

intended to be made mandatory in future RVB profiles, but are listed

as RVA23U64 development options as they are intended to become

mandatory in future RVA profiles.

以下是 RVB23U64 的 expansion options，因为它们不打算在未来的 RVB profile 中强制，但作为 RVA23U64 的开发选项列出，因为它们打算在未来的 RVA profile 中变为强制

• Zvbc Vector carryless multiplication.

Zvbc 矢量无进位乘法

Transitory Options

There are no transitory options in RVB23U64.

RVB23U64 中没有 transitory options

RVB23U64 Recommendations

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

十分推荐实现在尝试执行未实现的操作码时引发非法指令异常

RVB23S64 Profile

The RVB23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVB23S64 is based on privileged architecture version 1.13.

RVB23S64 profile 指定了 64 位应用处理器中 s-mode 执行环境可用的 ISA 特性。RVB23S64 基于特权架构版本 1.13

NOTE: Priv 1.13 is still being defined.

NOTE：Priv 1.13 仍在定义中

RVB23S64 Mandatory Base

RV64I is the mandatory base ISA for RVB23S64 and is little-endian.

The ECALL instruction operates as per the unprivileged architecture

specification. An ECALL in user mode causes a contained trap to

supervisor mode. An ECALL in supervisor mode causes a requested

trap to the execution environment.

RV64I 是 RVB23S64 的强制基本 ISA，并且是小端的。ECALL 指令按照非特权架构规范运行。在用户模式下的 ECALL 导致进入 s-mode 的 contained trap。在 s-mode 下的 ECALL 导致进入执行环境的 trap。

RVB23S64 Mandatory Extensions

The following unprivileged extensions are mandatory:

以下非特权扩展是强制的：

• The RVB23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVB23U64.

RVB23S64 强制的非特权扩展包括 RVB23U64 中的所有强制非特权扩展。

• Zifencei Instruction-Fetch Fence.

NOTE: Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVB23 application processors. A new instruction-cache coherence mechanism is under development (tentatively named Zjid) which might be added as an option in the future.

NOTE: Zifencei 是强制的，因为它是在 RVB23 应用处理器中支持指令缓存一致性的唯一标准方式。正在开发一种新的指令缓存一致性机制（暂时命名为 Zjid），可能会在未来作为选项添加。

The following privileged extensions are mandatory, and are also mandatory in RVA23S64.

以下 privileged extensions 是强制的，也是 RVA23S64 中强制的

• Ss1p13 Supervisor architecture version 1.13.

NOTE: Ss1p13 supersedes Ss1p12 but is not yet ratified.

NOTE：Ss1p13 取代了 Ss1p12，但尚未获得批准。

• Svnapot NAPOT translation contiguity.

Svnapot NAPOT translation 连续性

NOTE: Svnapot is very low cost to provide, so is made mandatory even

in RVB.

NOTE: Svnapot 的成本非常低，因此即使在 RVB 中也是强制的。

• Svbare The satp mode Bare must be supported.

Svbare 裸机模式下必须支持 satp

• Sv39 Page-Based 39-bit Virtual-Memory System.

Sv39 基于页的 39 位虚拟内存系统

• Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.

Svade 当 A 位清除时访问页面或当 D 位清除时写入页面时，引发页面错误异常

• Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.

Ssccptr 具备 cacheability 和 coherence PMAs 的主存储区域必须支持硬件页表读取

• Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.

Sstvecd stvec.MODE 必须能够保存值 0（Direct）。当 stvec.MODE=Direct 时，stvec.BASE 必须能够保存任何有效的四字节对齐地址

• Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions.For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.

Sstvala 对于加载、存储和指令页面错误、访问错误和不对齐异常，以及除了由 EBREAK 或 C.EBREAK 指令执行引起的断点异常之外的断点异常，必须使用故障虚拟地址写入 stval。对于虚拟指令和非法指令异常，stval 必须使用故障指令写入

• Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.

Sscounterenw 对于任何不是只读零的 hpmcounter，scounteren 中的相应位必须可写

• Svpbmt Page-based memory types.

Svpbmt 基于页的内存类型

• Svinval Fine-grained address-translation cache invalidation.

Svinval 细粒度地址转换缓存失效

• Sstc supervisor-mode timer interrupts.

Sstc s-mode 定时器中断

• Sscofpmf Count overflow and mode-based filtering.

Sscofpmf 计数溢出和基于模式的过滤

• Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).

Ssu64xl sstatus.UXL 必须能够保存值 2（即，必须支持 UXLEN=64）

RVB23S64 Optional Extensions

RVB23S64 has the same unprivileged options as RVB23U64,

The privileged options in RVB23S64 are listed in the following

sections.

RVB23S64 与 RVB23U64 具有相同的 unprivileged options，RVB23S64 中的 privileged options 列在以下章节

Localized Options

There are no privileged localized options in RVB23S64.

RVB23S64 中没有 privileged localized options

Development Options

There are no privileged development options in RVB23S64.

RVB23S64 中没有 privileged development options

Expansion Options

The following are privileged expansion options in RVB23S64, but are

mandatory in RVA23S64:

以下是 RVB23S64 中的 privileged expansion options，但在 RVA23S64 中是强制的：

• Ssnpm Pointer masking, with senvcfg.PMM supporting at minimum, settings PMLEN=0 and PMLEN=7.

Ssnpm 指针掩码，senvcfg.PMM 必须至少支持设置 PMLEN=0 和 PMLEN=7

• Sha The augmented hypervisor extension.

Sha 增强的 hypervisor 扩展

When the hypervisor extension is implemented, the following are also mandatory:

当 hypervisor extension 被实现时，以下也是强制的：

• If the hypervisor extension is implemented and pointer masking (Ssnpm) is supported then henvcfg.PMM must support at minimum, settings PMLEN=0 and PMLEN=7.

如果 hypervisor extension 被实现并且支持 pointer masking（Ssnpm），则 henvcfg.PMM 必须至少支持设置 PMLEN=0 和 PMLEN=7

The following are privileged expansion options in RVB23S64 that are

also privileged expansion options in RVA23S64:

以下是 RVB23S64 中的 privileged expansion options，也是 RVA23S64 中的 privileged expansion options：

• Sv48 Page-based 48-bit virtual-memory system.

Sv48 基于页的 48 位虚拟内存系统

• Sv57 Page-based 57-bit virtual-memory system.

Sv57 基于页的 57 位虚拟内存系统

• Svadu Hardware A/D bit updates.

Svadu 硬件 A/D 位更新

• Zkr Entropy CSR.
• Sdtrig Debug triggers.

Sdtrig 调试触发器

• Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.

Ssstrict 没有不符合规范的扩展。在标准或保留的编码空间中尝试执行未实现的操作码或访问未实现的 CSR 会引发非法指令异常，导致进入 s-mode 的 contained trap

NOTE: Ssstrict does not prescribe behavior for the custom encoding

spaces or CSRs.

NOTE：Ssstrict 不规定自定义编码空间或 CSR 的行为。

NOTE: Ssstrict definition applies to the execution environment claiming to be RVA23-compatible, which must have the hypervisor extension. That execution environment will take a contained trap to supervisor-mode (however that trap is implemented, including, but not limited to, emulation/delegation in the outer execution environment). Ssstrict (and all the other RVA23 mandates and options) do not apply to any guest VMs run by a hypervisor. An RVA23 hypervisor can provide guest VMs that are also RVA23-compatible but with an expanded set of emulated standard instructions. An RVA23 hypervisor can also choose to implement guest VMs that are not RVA23 compatible (e.g., lacking H, or only RVA20).

NOTE: Ssstrict 适用于符合 RVA23 的执行环境，该执行环境必须具有 hypervisor 扩展。该执行环境将进入 s-mode 的 contained trap（包括但不限于在外部执行环境中的模拟/委托）。Ssstrict（以及所有其他 RVA23 强制和选项）不适用于由 hypervisor 运行的任何 guest VM。RVA23 hypervisor 可以提供符合 RVA23 的 guest VM，但具有扩展的模拟标准指令集。RVA23 hypervisor 也可以选择实现不符合 RVA23 的 guest VM（例如，缺少 H，或仅 RVA20）。

• Svvptc Transitions from invalid to valid PTEs will be visible in bounded time without an explicit memory-management fence.

Svvptc 从无效到有效的 PTE 的转换将在有界时间内可见，而无需显式的内存管理栅栏

• Sspm Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

Sspm s-mode 指针掩码，s-mode 执行环境提供一种选择 PMLEN=0 和 PMLEN=7 的方法

RVB23S64 Recommendations

• Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes.
• 十分推荐实现在尝试执行未实现的操作码时引发非法指令异常。

Glossary of ISA Extensions

The following unprivileged ISA extensions are defined in Volume I

of the https://github.com/riscv/riscv-isa-manualRISC-V Instruction Set Manual.

• M Extension for Integer Multiplication and Division
• A Extension for Atomic Instructions
• F Extension for Single-Precision Floating-Point
• D Extension for Double-Precision Floating-Point
• H Hypervisor Extension
• Q Extension for Quad-Precision Floating-Point
• C Extension for Compressed Instructions
• B Extension for Bit Manipulation
• V Extension for Vector Computation
• Zifencei Instruction-Fetch Fence Extension
• Zicsr Extension for Control and Status Register Access
• Zicntr Extension for Basic Performance Counters
• Zihpm Extension for Hardware Performance Counters
• Zihintpause Pause Hint Extension
• Zfh Extension for Half-Precision Floating-Point
• Zfhmin Minimal Extension for Half-Precision Floating-Point
• Zfinx Extension for Single-Precision Floating-Point in x-registers
• Zdinx Extension for Double-Precision Floating-Point in x-registers
• Zhinx Extension for Half-Precision Floating-Point in x-registers
• Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers
• Zba Address Computation Extension
• Zbb Bit Manipulation Extension
• Zbc Carryless Multiplication Extension
• Zbs Single-Bit Manipulation Extension
• Zk Standard Scalar Cryptography Extension
• Zkn NIST Cryptography Extension
• Zknd AES Decryption Extension
• Zkne AES Encryption Extension
• Zknh SHA2 Hashing Extension
• Zkr Entropy Source Extension
• Zks ShangMi Cryptography Extension
• Zksed SM4 Block Cypher Extension
• Zksh SM3 Hashing Extension
• Zkt Extension for Data-Independent Execution Latency
• Zicbom Extension for Cache-Block Management
• Zicbop Extension for Cache-Block Prefetching
• Zicboz Extension for Cache-Block Zeroing
• Zawrs Wait-on-reservation-set instructions
• Zacas Extension for Atomic Compare-and-Swap (CAS) instructions
• Zabha Extension for Byte and Halfword Atomic Memory Operations
• Zbkb Extension for Bit Manipulation for Cryptography
• Zbkc Extension for Carryless Multiplication for Cryptography
• Zbkx Crossbar Permutation Extension
• Zvbb - Vector Basic Bit-manipulation
• Zvbc - Vector Carryless Multiplication
• Zvkng - NIST Algorithm Suite with GCM
• Zvksg - ShangMi Algorithm Suite with GCM
• Zvkt - Vector Data-Independent Execution Latency

The following privileged ISA extensions are defined in Volume II of the RISC-V Instruction Set Manual.

• Sv32 Page-based Virtual Memory Extension, 32-bit
• Sv39 Page-based Virtual Memory Extension, 39-bit
• Sv48 Page-based Virtual Memory Extension, 48-bit
• Sv57 Page-based Virtual Memory Extension, 57-bit
• Svpbmt, Page-Based Memory Types
• Svnapot, NAPOT Translation Contiguity
• Svinval, Fine-Grained Address-Translation Cache Invalidation
• Hypervisor Extension
• Sm1p11, Machine Architecture v1.11
• Sm1p12, Machine Architecture v1.12
• Ss1p11, Supervisor Architecture v1.11
• Ss1p12, Supervisor Architecture v1.12
• Ss1p13, Supervisor Architecture v1.13
• Sstc Extension for Supervisor-mode Timer Interrupts
• Sscofpmf Extension for Count Overflow and Mode-Based Filtering
• Smstateen/Ssstateen Extension for State-enable
• Svvptc Obviating Memory-management Instructions after Marking PTEs valid
• Svadu Hardware Updating of A/D Bits

The following extensions have not yet been incorporated into the RISC-V

Instruction Set Manual; the hyperlinks lead to their separate specifications.

• Zve32x Extension for Embedded Vector Computation (32-bit integer)
• Zve32f Extension for Embedded Vector Computation (32-bit integer, 32-bit FP)
• Zve32d Extension for Embedded Vector Computation (32-bit integer, 64-bit FP)
• Zve64x Extension for Embedded Vector Computation (64-bit integer)
• Zve64f Extension for Embedded Vector Computation (64-bit integer, 32-bit FP)
• Zve64d Extension for Embedded Vector Computation (64-bit integer, 64-bit FP)
• Ziccif: Main memory supports instruction fetch with atomicity requirement
• Ziccrse: Main memory supports forward progress on LR/SC sequences
• Ziccamoa: Main memory supports all atomics in A
• Ziccamoc Main memory supports atomics in Zacas
• Zicclsm: Main memory supports misaligned loads/stores
• Zama16b: Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.
• Za64rs: Reservation set size of at most 64 bytes
• Za128rs: Reservation set size of at most 128 bytes
• Zic64b: Cache block size is 64 bytes
• Svbare: Bare mode virtual-memory translation supported
• Svade: Raise exceptions on improper A/D bits
• Ssccptr: Main memory supports page table reads
• Sscounterenw: Support writeable enables for any supported counter
• Sstvecd: stvec supports Direct mode
• Sstvala: stval provides all needed values
• Ssu64xl: UXLEN=64 must be supported
• Sha: Augmented hypervisor extension
• Shcounterenw: Support writeable enables for any supported counter
• Shvstvala: vstval provides all needed values
• Shtvala: htval provides all needed values
• Shvstvecd: vstvec supports Direct mode
• Shvsatpa: vsatp supports all modes supported by satp
• Shgatpa: SvNNx4 mode supported for all modes supported by satp, as well as Bare
• Ssstrict: Unimplemented reserved encodings raise illegal instruction exceptions and no non-conforming extension are present

With the help of github Copilot and Gemini 2 flash