Xilinx FPGA程序升级

STARTUPE2 #(
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation
)
STARTUPE2_inst
(
.CFGCLK(), // 1-bit output: Configuration main clock output
.CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output
.EOS(), // 1-bit output: Active high output signal indicating the End Of Startup.
.PREQ(), // 1-bit output: PROGRAM request to fabric output
.CLK(0), // 1-bit input: User start-up clock input
.GSR(0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
.GTS(0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
.KEYCLEARB(1), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
.PACK(1), // 1-bit input: PROGRAM acknowledge input
.USRCCLKO(flash_clk), // 1-bit input: User CCLK input**将SPI的时钟链接到这里**
.USRCCLKTS(0), // 1-bit input: User CCLK 3-state enable input
.USRDONEO(1), // 1-bit input: User DONE pin output control
.USRDONETS(1) // 1-bit input: User DONE 3-state enable outpu
);

ICAPE2 #(
   .DEVICE_ID(0'h3651093    ),      // Specifies the pre-programmed Device ID value to be used for simulation
   .ICAP_WIDTH            ("X32"      ),      // Specifies the input and output data width.
   .SIM_CFG_FILE_NAME    ("C:\\VivadoPrj\\FPGAUartProgram\\7Serial\\7Serial_A7\\7Serial_A7.runs\\impl_1\\OnlineProgram_top.bit"      )       // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation model.                                
)
ICAPE2_inst (
   .O        (ICAPE2_O       ),  // 32-bit output: Configuration data output bus
   .CLK        (ICAPE2_CLK     ),  // 1-bit input: Clock Input
   .CSIB    (ICAPE2_CSIB    ),  // 1-bit input: Active-Low ICAP Enable
   .I        (ICAPE2_I       ),  // 32-bit input: Configuration data input bus
   .RDWRB    (ICAPE2_RDWRB   )   // 1-bit input: Read/Write Select input
);

ICAPE2_I[0]         <=  icape2_data_r[7];
ICAPE2_I[1]         <=  icape2_data_r[6];
ICAPE2_I[2]         <=  icape2_data_r[5];
ICAPE2_I[3]         <=  icape2_data_r[4];
ICAPE2_I[4]         <=  icape2_data_r[3];
ICAPE2_I[5]         <=  icape2_data_r[2];
ICAPE2_I[6]         <=  icape2_data_r[1];
ICAPE2_I[7]         <=  icape2_data_r[0];


ICAPE2_I[8]      <= icape2_data_r[15];
ICAPE2_I[9]      <= icape2_data_r[14];
ICAPE2_I[10]     <=  icape2_data_r[13];
ICAPE2_I[11]     <=  icape2_data_r[12];
ICAPE2_I[12]     <=  icape2_data_r[11];
ICAPE2_I[13]     <=  icape2_data_r[10];
ICAPE2_I[14]     <=  icape2_data_r[9];
ICAPE2_I[15]     <=  icape2_data_r[8];

ICAPE2_I[16]     <=  icape2_data_r[23];
ICAPE2_I[17]     <=  icape2_data_r[22];
ICAPE2_I[18]     <=  icape2_data_r[21];
ICAPE2_I[19]     <=  icape2_data_r[20];
ICAPE2_I[20]     <=  icape2_data_r[19];
ICAPE2_I[21]     <=  icape2_data_r[18];
ICAPE2_I[22]     <=  icape2_data_r[17];
ICAPE2_I[23]     <=  icape2_data_r[16];


ICAPE2_I[24]     <=  icape2_data_r[31];
ICAPE2_I[25]     <=  icape2_data_r[30];
ICAPE2_I[26]     <=  icape2_data_r[29];
ICAPE2_I[27]     <=  icape2_data_r[28];
ICAPE2_I[28]     <=  icape2_data_r[27];
ICAPE2_I[29]     <=  icape2_data_r[26];
ICAPE2_I[30]     <=  icape2_data_r[25];
ICAPE2_I[31]     <=  icape2_data_r[24];

set cclk_delay 6.7
# Following are the SPI device parameters
# Max Tco
set tco_max 7
# Min Tco
set tco_min 1
# Setup time requirement
set tsu 2
# Hold time requirement
set th 3
# Following are the board/trace delay numbers
# Assumption is that all Data lines are matched
set tdata_trace_delay_max 0.25
set tdata_trace_delay_min 0.25
set tclk_trace_delay_max 0.2
set tclk_trace_delay_min 0.2
### End of user provided delay numbers
# This is to ensure min routing delay from SCK generation to STARTUP input
# User should change this value based on the results
# Having more delay on this net reduces the Fmax
# Following constraint should be commented when the STARTUP block is disabled
set_max_delay 1.5 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO] -datapath_only
set_min_delay 0.1 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO]
# Following command creates a divide by 2 clock
# It also takes into account the delay added by the STARTUP block to route the CCLK
# This constraint is not needed when the STARTUP block is disabled
# The following constraint should be commented when the STARTUP block is disabled
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_pins -hierarchical *USRCCLKO] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay]
# Enable the following constraint when STARTUP block is disabled
#create_generated_clock -name clk_virt -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
# Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
# Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
# Data is captured into SPI on the following rising edge of SCK
# Data is driven by the IP on alternate rising_edge of the ext_spi_clk
set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min -$th - $tclk_trace_delay_max] [get_ports IO*_IO];
set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck