SMP多核启动

# echo 0 > /sys/devices/system/cpu/cpu1/online

# echo 1 > /sys/devices/system/cpu/cpu1/online

struct smp_operations {
#ifdef CONFIG_SMP
    /*
     * Setup the set of possible CPUs (via set_cpu_possible)
     */
    void (*smp_init_cpus)(void);
    /*
     * Initialize cpu_possible map, and enable coherency
     */
    void (*smp_prepare_cpus)(unsigned int max_cpus);

    /*
     * Perform platform specific initialisation of the specified CPU.
     */
    void (*smp_secondary_init)(unsigned int cpu);
    /*
     * Boot a secondary CPU, and assign it the specified idle task.
     * This also gives us the initial stack to use for this CPU.
     */
    int  (*smp_boot_secondary)(unsigned int cpu, struct task_struct *idle);
#ifdef CONFIG_HOTPLUG_CPU
    int  (*cpu_kill)(unsigned int cpu);
    void (*cpu_die)(unsigned int cpu);
    int  (*cpu_disable)(unsigned int cpu);
#endif
#endif
};

DT_MACHINE_START(VEXPRESS DT,"ARM-Versatile Express)
.dt_compat = v2m_dt_match,
.smp = smp_ops(express_smp_ops),
.map_io = v2m_dt_map_io,
MACHINE_END

static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
{
    /*
     * Initialise the present map, which describes the set of CPUs
     * actually populated at the present time.
     */
    if (ct_desc)
        ct_desc->smp_enable(max_cpus);
    else
        vexpress_dt_smp_prepare_cpus(max_cpus);

    /*
     * Write the address of secondary startup into the
     * system-wide flags register. The boot monitor waits
     * until it receives a soft interrupt, and then the
     * secondary CPU branches to this address.
     */
    vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
}

void __init v2m_flags_set(u32 data)
{
    writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
    writel(data, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
}

/*
 * Write pen_release in a way that is guaranteed to be visible to all
 * observers, irrespective of whether they're taking part in coherency
 * or not.  This is necessary for the hotplug code to work reliably.
 */
static void __cpuinit write_pen_release(int val)
{
    pen_release = val;
    smp_wmb();
    __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
    outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
}

int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
    unsigned long timeout;

    /*
     * Set synchronisation state between this boot processor
     * and the secondary one
     */
    spin_lock(&boot_lock);

    /*
     * This is really belt and braces; we hold unintended secondary
     * CPUs in the holding pen until we're ready for them.  However,
     * since we haven't sent them a soft interrupt, they shouldn't
     * be there.
     */
    write_pen_release(cpu_logical_map(cpu));

    /*
     * Send the secondary CPU a soft interrupt, thereby causing
     * the boot monitor to read the system wide flags register,
     * and branch to the address found there.
     */
    arch_send_wakeup_ipi_mask(cpumask_of(cpu));

    timeout = jiffies + (1 * HZ);
    while (time_before(jiffies, timeout)) {
        smp_rmb();
        if (pen_release == -1)
            break;

        udelay(10);
    }

    /*
     * now the secondary core is starting up let it run its
     * calibrations, then wait for it to finish
     */
    spin_unlock(&boot_lock);

    return pen_release != -1 ? -ENOSYS : 0;
}

/*
 * Realview/Versatile Express specific entry point for secondary CPUs.
 * This provides a "holding pen" into which all secondary cores are held
 * until we're ready for them to initialise.
 */
ENTRY(versatile_secondary_startup)
    mrc p15, 0, r0, c0, c0, 5
    bic r0, #0xff000000
    adr r4, 1f
    ldmia   r4, {r5, r6}
    sub r4, r4, r5
    add r6, r6, r4
pen:    ldr r7, [r6]
    cmp r7, r0
    bne pen

    /*
     * we've been released from the holding pen: secondary_stack
     * should now contain the SVC stack for this core
     */
    b   secondary_startup

    .align
1:  .long   .
    .long   pen_release
ENDPROC(versatile_secondary_startup)

void __cpuinit versatile_secondary_init(unsigned int cpu)
{
    /*
     * let the primary processor know we're out of the
     * pen, then head off into the C entry point
     */
    write_pen_release(-1);

    /*
     * Synchronise with the boot thread.
     */
    spin_lock(&boot_lock);
    spin_unlock(&boot_lock);
}

timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
    smp_rmb();
    if (pen_release == -1)
        break;

    udelay(10);
}