偶数倍频

module clk_div_16(

clk_in,rst_n,clk_out
    );
input clk_in;
input rst_n;
output clk_out;
reg [2:0]cnt;
reg clk_out_t;
always @( posedge clk_in) begin
if(!rst_n) begin
cnt<=3'b000;
clk_out_t<=1'b0;
end
else begin
if(cnt==3'b111) begin
cnt<=3'b000;
clk_out_t<=~clk_out_t;
end
else begin
cnt<=cnt+3'b001;
end
end
end
assign clk_out=clk_out_t;
Endmodule